1. Field of the Invention
The present invention relates generally to phase alignment techniques and more particularly to phase aligning two clock signals using programmable phase adjustment circuitry.
2. Description of the Related Art
The first generations of fiber-optic systems in the public telephone network used proprietary architectures, equipment, line codes, multiplexing formats, and maintenance procedures. These transmission systems were asynchronous, with each terminal or hub in the network running on a different clock. In digital transmission, a clock refers to a series of repetitive pulses that keep the bit rate of data constant and indicate the location of ones and zeroes in a data stream. Since the clocks in the first generation systems were not synchronized, large variations occurred in the clock rate and thus the signal bit rate.
The synchronous optical network (SONET) standard was developed to provide a synchronous optical system that enables the interconnection of equipment from different suppliers without causing large variations in the clock rate and the signal bit rate. The SONET standard defines a technology for carrying many signals of different capacities through a synchronous, flexible, optical hierarchy. SONET defines a set of synchronous signals, including optical carrier (OC) levels and electrically equivalent synchronous transport signals (STSs) for the fiber-optic-based transmission hierarchy. A similar standard to SONET is the Synchronous Digital Hierarchy (SDH) which is the optical fiber standard predominantly used in Europe. There are only minor differences between the two standards. Accordingly, hereinafter any reference to the term SONET refers to both SDH and SONET networks, unless otherwise noted.
In a set of synchronous signals, digital transitions occur at exactly the same rate. There can, however, be a phase difference between the transitions of the two signals, which must lie within specified limits. The phase differences can be due to propagation time delays or jitter introduced into the transmission network. In the synchronous network defined by SONET, all clocks are traceable to one primary reference clock (PRC), also referred to as a Stratum 1 atomic clock. The accuracy of the PRC is better than +xe2x88x921 in 1011.
SONET utilizes a byte-interleaved multiplexing scheme. Mulitplexing enables one physical medium to carry multiple signals. Byte-interleaving simplifies multiplexing and offers end-to-end network management. Each STS is transmitted on a link at regular time intervals (for example, 125 microseconds) and grouped into frames. See Bellcore Generic Requirements document GR-253-CORE (Issue 2, December 1995), hereinafter referred to as xe2x80x9cSONET Specification,xe2x80x9d and incorporated herein by reference for all purposes. The first step in the SONET multiplexing process involves the generation of the lowest level or base signal. In SONET, this base signal is referred to as synchronous transport signalxe2x80x94level 1, or simply STS-1, which operates at 51.84 Mbps. Higher-level signals are integer multiples of STS-1, creating the family of STS-N signals in Table 1. An STS-N signal is composed of N byte-interleaved STS-1 signals. Table 1 also includes the optical counterpart for each STS-N signal, designated optical carrier level N (OC-N).
SONET organizes STS data streams into frames, consisting of transport overhead and a synchronous payload envelope. The overhead consists of information that allows the network to operate and allow communications between a network controller and nodes. The transport overhead includes framing information and pointers, and performance monitoring, communications and maintenance information. The synchronous payload envelope is the data to be transported throughout the network, from node to node until the data reaches its destination.
SONET utilizes pointers to accommodate differences in the reference source frequencies and phase wander and to prevent frequency differences during synchronization failures. Adjustments to the pointers compensate for frequency and phase variations. The use of pointers avoids the delays and loss of data associated with the transmission of large amounts of data. A pointer is an offset value that points to the byte where the payload begins in the frame. The pointer allows the payload to be separated from the transport overhead. If there are any frequency or phase variations between the frame and the associated payload, the pointer value will be increased or decreased accordingly to maintain synchronization. When there is a difference in phase or frequency, the pointer value is adjusted. To accomplish this, a process known as byte stuffing is used. In other words, the payload pointer indicates where in the frame the payload starts, and the byte-stuffing allows dynamic alignment of the payload in case the payload slips in time.
Routers, cross-connect systems, and other network nodes are commonly employed in the telecommunication network synchronization hierarchy. The network is organized with a master-slave relationship with clocks of the higher level nodes feeding timing signals to clocks of the lower-level nodes. All nodes can be traced up to the primary reference source, a Stratum 1 atomic clock with extremely high stability and accuracy. The internal clock of a SONET hub derives the hub""s timing signal from a Building Integrated Timing Supply (BITS) clock used by switching systems and other equipment. The hub serves as a master for other SONET nodes, providing timing on the hubs""outgoing OC-N signal. Current standards specify that a SONET network must be able to derive the internal timing from a Stratum 3 or higher clock. A SONET optical cross connect accepts various optical carrier rates, accesses the STS-1 signals, and switches at this level.
A common feature of a telecommunication system node is the redundancy built into the architecture. Redundancy refers to providing a duplicate set of circuitry that functions as a backup system in case of a failure. At any given time, one set of circuitry is designated as active while the other is designated standby. When a failure occurs in a portion of the active circuitry, the corresponding standby circuitry is switched to active and the active circuitry is switched to standby, allowing the circuitry to be repaired without bringing the system into a non-operational state. In addition, the redundancy in the architecture provides for other activities, such as routine maintenance and circuit or software upgrades to occur while allowing the system to continue functioning. Although circuitry is designated as either active or standby, both circuits can be fully operational. The outputs of the redundant circuits are monitored and compared for performance and failures.
In a SONET hub, clocks are derived from the BITS clock and then distributed throughout the hub. Processors, electrical components, control signals, etc. need clock signals to run properly. To provide clock inputs to all of these circuits, the original clock signal needs to be duplicated, typically via clock trees utilizing layers of clock buffers. Clock buffering, as well as loading, routing, temperature, and voltage differences lead to phase misalignment between the derived clock signals. Routing, duplication and selection of clock signals due to the redundancy of the architecture further increases the phase difference between clock signals.
Unless compensated for, the clock operating the active circuitry can have a large phase difference from the clock operating the standby circuitry. In some designs, the phase difference does not affect the operation of the system except when switching between active and standby circuitry. The phase difference, if not corrected, can cause data loss. To avoid such errors, the standby clock must be phase-aligned with the active clock prior to switching the standby circuitry to active.
FIG. 1 illustrates a prior art circuit for synchronizing two clocks. The synchronization of two clock signals is typically performed by a phase locked loop (xe2x80x9cPLLxe2x80x9d) or other analog circuitry. Two clocks, labeled CLK A and CLK B, are fed into a multiplexer 105. One of CLK A or CLK B is selected as an ACTIVE CLK by multiplexer 105 and is fed into a phase detector 110 with a FEEDBACK CLK. Phase detector 110 detects the phase difference between ACTIVE CLK and FEEDBACK CLK. The phase difference output is sent through a low pass filter 120 and an amplifier 130 and controls the frequency of a voltage controlled oscillator (VCO) 140. The phase difference output that is generated by phase detector 110 is used to retune the frequency of VCO 140 whenever ACTIVE CLK deviates from FEEDBACK CLK, such as when switching multiplexer 105 from selecting CLK A or CLK B as ACTIVE CLK. The frequency of VCO 140 is driven toward the frequency of ACTIVE CLK. FEEDBACK CLK tracks the phase of ACTIVE CLK and locks to ACTIVE CLK through the feed back loop. The frequency of FEEDBACK CLK is adjusted during the synchronization process. Because FEEDBACK CLK is typically used to clock the active circuitry, the change in frequency during the synchronization process can cause a loss of data.
In an optical cross-connect supporting the SONET standard, the hub clocks are used to control pointers and timing within a frame and thus cannot withstand large changes in frequency. Using a PLL to synchronize clocks causes a change in frequency of the feedback clock during synchronization. The change in frequency can result in data loss.
Rather than using a PLL to phase align clock signals, a phase adjustment can be added to a standby clock using digital circuitry. Typically, the phase difference between two clocks is measured using a much higher frequency clock. For example, for two clocks operating at 50 MHz, a 10 GHz clock can be used to count the amount of time between a rising edge of the first clock signal and the next rising edge of the second clock signal to determine the phase misalignment. The use of a 10 GHz clock provides phase alignment within approximately 100 ps (picoseconds). The use of a much higher clock frequency is often limited due to technology constraints. For example, in an FPGA (Field Programmable Gate Array), a 50 MHz clock is easily handled by the CMOS technology. However, the CMOS technology in an FPGA cannot handle a clock frequency as high as 10 GHz. Therefore, the phase adjustment circuitry can be located outside the FPGA or more expensive technology can be used.
The design of digital circuitry to provide a variable amount of phase adjustment is difficult due to the need to place restrictions on the placement and routing of the components in a digital device. Adherence to strict layout parameters often requires costly and time consuming placement and routing of the phase adjustment circuitry and often leads to undesirable delay of any other circuitry in the digital device.
A method and apparatus for phase adjusting a clock signal is needed that provides for a variable amount of phase adjustment, that will not change signal""s frequency, and that can be accomplished in a cost effective manner.
An apparatus, method, communications device and computer readable medium for phase aligning two clocks and providing a graceful switch between active and standby circuitry is disclosed.
The apparatus has a reporting circuit configured to receive a measured phase difference between a first clock signal and a second clock signal, a selection circuit configured to select a configurable phase adjustment according to the measured phase difference, and a granularity adjustment circuit configured to add the configurable phase adjustment to the first clock signal generating a phase adjusted clock signal.
The communications device has a first timing card having an input to receive a BITS clock signal configured to generate a derived clock signal, a second timing card having an input to receive the BITS clock signal configured to generate a derived clock signal, and a shelf controller configured to receive the derived clock signal and the derived clock signal from the second timing card. The shelf controller has a reporting circuit configured to receive a measured phase difference between a first clock signal and a second clock signal, a selection circuit configured to select a configurable phase adjustment according to the measured phase difference and a granularity adjustment circuit configured to add the configurable phase adjustment to the first clock signal generating a phase adjusted clock signal.
The method comprises receiving a first measured phase difference between a first clock signal and a second clock signal, comparing the first measured phase difference to a maximum allowable phase difference value, adding a phase adjustment to the first clock signal if the measured phase difference is greater than the maximum allowable phase difference value, and repeating receiving the first measured phase difference, comparing the first measured phase difference and adding the phase adjustment until the measured phase difference is not greater than the maximum allowable phase difference value.
The computer readable medium has a set of instructions for enabling a system to receive a first measured phase difference between a first clock signal and a second clock signal, compare the first measured phase difference to a maximum allowable phase difference value, add a phase adjustment to the first clock signal if the measured phase difference is greater than the maximum allowable phase difference value, and repeat receiving the first measured phase difference, comparing the first measured phase difference and adding the phase adjustment until the measured phase difference is not greater than the maximum allowable phase difference value.
In other embodiments of the present invention, the apparatus and communications device further comprise a second selection circuit for selecting a second configurable phase adjustment to be added to the first clock signal according to the measured phase difference, a second granularity adjustment circuit for adding the second configurable phase adjustment to the first clock signal, and wherein a maximum amount of phase adjustment able to be added to the first clock signal by the granularity adjustment circuit is greater than a maximum amount of phase adjustment able to be added by the second granularity adjustment circuit.
In other embodiments of the present invention, the apparatus and communications device have a granularity adjustment circuit comprising a first plurality of phase adjustment elements, a second granularity adjustment circuit comprising a second plurality of phase adjustment elements, a third granularity adjustment circuit comprising a third plurality of phase adjustment elements and each of the phase adjustment elements from the first plurality has the ability to add a greater amount of phase adjustment to the first clock signal than each of the phase adjustment elements from the second plurality and each of the phase adjustment elements from the second plurality has the ability to add a greater amount of phase adjustment to the first clock signal than each of the phase adjustment elements from the third plurality.
In other embodiments of the invention, the method and computer readable medium further comprise receiving a second measured phase difference between a first clock signal and a second clock signal, comparing the second measured phase difference to a maximum allowable medium phase difference value, adding a medium phase adjustment to the first clock signal if the second measured phase difference is greater than the maximum allowable medium phase difference value, and repeating the receiving the second measured phase difference, comparing the second measured phase difference, and adding the medium phase adjustment until the second measured phase difference is not greater than the maximum allowable medium phase difference value.
The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. As will also be apparent to one of skill in the art, the operations disclosed herein may be implemented in a number of ways, and such changes and modifications may be made without departing from this invention and its broader aspects. Other aspects, inventive features, and advantages of the present invention, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth below.